I doubt that would actually be useful with overclocking. I don't know the arch of the modern PC well enough to say with 100% confidence, but on embedded arches, the RAM has the parity bits checked when they get placed on the bus. If the error happens on data retrieval(or was already present) , then the ECC saves you, but if it happen anywhere else... not really? I don't know if.. ALU's for example automatically include the parity bits in the computation.
The GTX 1080 has GDDR5X, which has ECC. I was able to dial in my memory OC on that card by increasing the clock then running memory throughput benchmarks until the throughput was maxed out. At the point where errors start the theroughput would decrease, but nothing would fail.
Assuming stationary processes this is pretty nice. Maybe bump back 5% for margin.
I believe that's inside the chip, much like DDR5. However that doesn't help if there's an error introduced by the packages, pin, board traces, CPU pins, or CPU.
